This invention relates to a semiconductor device and, more particularly, to a semiconductor device having interconnections and a process for fabricating
Semiconductor manufacturers have progressively increased component elements integrated on a semiconductor substrate. While the manufacturers is fabricating the component elements on the semiconductor elements, various patterns are transferred to semiconductor/insulting layers forming a multiple-layered structure on the semiconductor substrate, and contact holes are formed in the inter-layered insulating layers. The contact holes are miniaturized together with the component elements, and, accordingly, have a large aspect ratio, i.e., the ratio of the depth to the diameter. The contact holes are filled with conductive material during the deposition for upper wirings, and upper conductive lines are electrically connected to lower conductive lines through the conductive material in the contact holes. Thus, the conductive lines are connected between the component elements on the different levels, and the component elements form in combination an integrated circuit.
Aluminum is popular to the semiconductor manufacturers as the conductive material. The aluminum is deposited through a sputtering, and the aluminum layer is patterned to the conductive lines through a photo-lithography and an etching. However, the aluminum is poor in step coverage, and the poor step coverage is causative of disconnection due to the large resistance. Even if the aluminum layer is patterned to the conductive lines without disconnection, the conductive lines are less durable. Namely, the conductive lines are exposed to the electro-migration at the poor step coverage, and are liable to be disconnected.
One of the approaches against the poor step coverage is to form contact plugs in the contact holes. A typical example of the contact plug is formed of tungsten. The tungsten plugs are formed as follows. First, contact holes are formed in an inter-layered insulting layer, and a barrier metal layers are formed on the inner surfaces of the contact holes. A titanium layer and a titanium nitride layer form in combination the barrier metal layer, and the titanium and the titanium nitride are deposited by using sputtering techniques. The titanium layer lowers the contact resistance to a lower semiconductor layer. On the other hand, the titanium nitride layer enhances the adhesion between the titanium layer and a tungsten plug, and prevents the lower semi-conductor layer from the tungsten diffused thereinto. The barrier metal layer defines a recess in the contact hole, and tungsten is deposited by using a chemical vapor deposition, which forms good step coverage. The tungsten fills the recess, and swells into a tungsten layer over the inter-layered insulating layer. The tungsten layer is uniformly etched without any mask, and a tungsten plug is left in the recess.
Although the tungsten plug fairly improves the step coverage, the titanium layer and the titanium nitride layer are hardly deposited to target thickness in miniature contact holes to be required for an ultra large-scale integration. If the titanium/titanium nitride layers do not have the target thickness, the contact resistance is increased, and/or the tungsten damages the component elements formed in the lower semiconductor layer.
In order to exactly control the titanium layer and the titanium nitride layer, a chemical vapor deposition is desirable. Especially, a chemical vapor deposition using a thermal reaction is the most appropriate for the titanium nitride layer from the view point of the step coverage, and is widely used for the barrier metal layer. Thus, the titanium, the titanium nitride and the tungsten are respectively deposited by using the three chemical vapor deposition techniques. However, the prior art process sequence is complicated, and the tungsten is costly. This results in increase of the production cost.
It is proposed to fill the recess with the titanium nitride deposited through the chemical vapor deposition technique. The tungsten plug is eliminated from the interconnection, because the titanium nitride forms fairly good step coverage.
FIGS. 1A to 1D show the prior art process. The prior art process starts with preparation of a silicon substrate 501 where a field oxide layer (not shown) is selectively grown. Silicon oxide or boro-phosphosilicate glass is deposited to 1.5 microns thick by using a chemical vapor deposition, and forms an inter-layered insulating layer 502. A photo-resist etching mask (not shown) is formed on the inter-layered insulating layer 502 by using the photo-lithography, and the inter-layered insulating layer 502 is selectively etched by using a dry etching. Then, a contact hole 503 is formed in the inter-layered insulating layer 502 as shown in FIG. 1A, and is 0.4 micron in diameter.
Subsequently, titanium is deposited over the entire surface of the resultant structure to thickness between 5 nanometers to 20 nanometers by using a plasma-assisted chemical vapor deposition, and forms a titanium layer 504. The titanium layer 504 conformably extends, and defines a recess in the contact hole 503. Titanium nitride is deposited over the entire surface of the resultant structure by using a thermal chemical vapor deposition. The titanium nitride fills the recess, and swells into a titanium nitride layer 505 of 0.4 micron thick. Thus, the contact hole 503 is perfectly filled with the titanium and the titanium nitride as shown in FIG. 1B.
Subsequently, the titanium nitride layer 505 and the titanium layer 504 are etched without any mask until the inter-layered insulating layer 502 is exposed again. Chlorine-containing etching gas is used in the dry etching. As a result, a titanium layer 504a and a piece of titanium nitride are left in the contact hole 503 as shown in FIG. 1C, and serve as a conductive plug.
Aluminum alloy is deposited over the entire surface of the resultant structure by using a sputtering, and forms an aluminum alloy layer. A photo-resist etching mask (not shown) is formed through the photo-lithography, and the aluminum alloy layer is selectively etched away by using a dry etching technique. An aluminum alloy strip 506 is formed on the inter-layered insulating layer 502 as shown in FIG. 1D.
Thus, the conductive plug is formed from the titanium layer 504 and the titanium nitride layer 505, and any tungsten is not used for the conductive plug. This results in reduction in production cost. However, a problem is encountered in the above-described prior art process in low production yield.
It is therefore an important object of the present invention to provide a process for fabricating a semiconductor device that is improved in production yield.
The present inventor investigated the defective products fabricated through the prior art process. The defective products were grouped into three classes. The first class had been rejected due to damage of the inter-layered insulating layer 502. The second class had been rejected due to contaminant, ad the third class had been rejected due to leakage current flowing into the silicon substrate 501 or impurity regions formed in the silicon substrate 501.
In the defective products grouped in the first class, the inter-layered insulating layers 502 were violently etched during the dry etching for patterning the titanium layer 504. The present inventor observed the titanium nitride layer 505, and found a lot of cracks therein and separation between the titanium nitride layer 505 and the titanium layer 504. The present inventor assumed that the inter-layered insulating layer 502 had been attacked by the etchant penetrating through the cracks and the gap between the titanium layer 504 and the titanium nitride layer 505.
In the defective products grouped into the second class, the contaminant was pieces of titanium nitride. The pieces of titanium nitride were assumed to be produced from the titanium nitride layer 505 due to the cracks and the separation.
In the defective products grouped into the third class, the silicon substrate 501 and the impurity regions were damaged by the etchant, and the titanium nitride layer 505 was also cracked and separated from the titanium layer 504.
Thus, all the defective products were derived from the cracks and the separation of the titanium nitride layer 505. The present inventor further investigated the titanium nitride layer 505, and found that the cracks and the separation were derived from large thermal stress exerted on the titanium nitride layer 505 and relatively small adhesion of the titanium nitride. In order to obtain good step coverage, it was necessary to deposit the titanium nitride to a large thickness at high temperature ambience. When the titanium nitride layer 505 was cooled to room temperature, large tensile stress was exerted on the titanium nitride layer 505 due to the difference in thermal expansion coefficient between the titanium and the titanium nitride. The tensile stress was equal to or greater than 2.5 GPa. Moreover, the titanium nitride was less adhesive to the titanium. In this situation, the large thermal stress was causative of the separation and a lot of cracks. The etchant had penetrated through the cracks and the gap, and damaged the inter-layered insulating layer 502 and the silicon substrate 501.
To accomplish the object, the present invention proposes to absorb the thermal stress by using a refractory metal silicide.
In accordance with one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, at least one circuit component fabricated on the semiconductor substrate, an inter-layered insulating structure formed on the semiconductor substrate and a wiring structure connected to the aforesaid at least one circuit component, and one of the aforesaid at least one circuit component and the wiring structure has a multi-layered structure including a refractory metal silicide and a refractory metal nitride laminated on each other.
In accordance with another aspect of the present invention, there is provided a process for fabricating a semiconductor device comprising the steps of a) preparing a semiconductor substrate, b) forming an inter-layered insulating layer over the semiconductor substrate, c) forming a hole in the inter-layered insulating layer, and d) forming a multi-layered conductive structure including a first refractory metal silicide layer and a first refractory metal nitride layer laminated on each other in the hole by using a chemical vapor deposition.
In accordance with yet another aspect of the present invention, there is provided a process for fabricating a semiconductor device, comprising the steps of a) preparing a semiconductor substrate, b) forming an inter-layered insulating layer over the semiconductor substrate, and c) forming a multi-layered conductive structure including a first refractory metal silicide layer and a first refractory metal nitride layer laminated on each other on the inter-layered insulating layer by using a chemical vapor deposition.